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1 multiphase pwm regulator for vr12 ddr memory systems ISL6353 the ISL6353 is a three-phase pwm buck regulator controller for vr12 ddr memory applications. the multi-phase implementation results in better system performance, superior thermal management, lower component cost and smaller pcb area. the ISL6353 has two integrated power mosfet drivers for implementing a cost effective and space saving power management solution. the pwm modulator of the ISL6353 is based on intersil?s robust ripple regulator? (r 3 ) technology. compared with the traditional multi-phase buck regulator, the r 3 modulator commands variable pwm switching frequency during lo ad transients, achieving faster transient response. r 3 also naturally goes into pulse frequency modulation operation in light load conditions to achieve higher light load efficiency. the ISL6353 is designed to be co mpletely compliant with vr12 specifications. the ISL6353 has a serial vid (svid) bus communicating with the cpu. the output can be programmed for 1-, 2- or 3-phase interleaved operation. the output voltage and power state can also be controlled independent of the serial vid bus. the ISL6353 has several other key features. it supports dcr current sensing with a sing le ntc thermistor for dcr temperature compensation or accu rate resistor current sensing. it also has remote voltage sense, adjustable switching frequency, current monitor, oc/ov protecti on and power-good. temperature monitor and thermal alert is available too. features ? vr12 serial communications bus ? precision voltage regulation - 5mv steps with vid fast/slow slew rates ? supports two current sensing methods - lossless inductor dcr current sensing - precision resistor current sensing ? programmable 1, 2 or 3-phase operation ? adaptive body diode conduction time reduction ? superior noise immunity and transient response ? pin programmable output voltage and power state mode ? output current monitor and thermal monitor ? differential remote voltage sensing ? high efficiency across entire load range ? programmable switching frequency ? resistor programmable vboot, power state operation, svid address setting, i max ? excellent dynamic current balance between phases ? ocp/woc, ovp, ot alert, pgood ? small footprint 40 ld 5x5 tqfn package ? pb-free (rohs compliant) applications ?ddr memory figure 1. fast transient response figure 2. ISL6353eval1z efficiency vs load comp 200mv/div vddq = 1.5v 50mv/div phase1/2/3 5v/div 1v/div 26a step load 20s/div 85 86 87 88 89 90 91 92 93 94 95 0 1020304050607080 load (a) 1.5v ps1 2ph ccm 1.5v ps0 1.5v ps2 1ph de 1.35vps0 1.35v ps1 2ph ccm 1.35vps2 1ph de efficiency (%) fn6897.0 september 15, 2011 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2011. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
ISL6353 2 september 15, 2011 fn6897.0 simplified application circuit us ing inductor dcr current sensing prog1 vdd vr_on sda p pgood vddq ISL6353 +5v dual ph2 isen1 sclk alert# boot1 ug1 ph1 lg1 isen2 boot2 ug2 ph2 lg2 +12v vr_hot# vset1 isen3 pwm3 +5v vcc vctrl pwm boot ugate phase lgate gnd isl6596 driver +12v ntc vin (5vsb/12v dual) gnd gnd prog2 vddp { vin gnd pad imon isump isumn ph1 ph2 ph3 vo1 vo2 vo3 ph1 ph3 vset2 +5v dual ph1 vo1 ph2 vo2 ph3 vo3 ovp addr rntc vin psi c c vsumn fb vccsense rtn vsssense vsen fb2 comp vw
ISL6353 3 september 15, 2011 fn6897.0 block diagram lg1 gnd vddp pgood driver ug1 ph1 boot1 driver lg2 gnd driver ug2 ph2 boot2 driver isen2 isen3 isen1 oc and woc protection ov protection isumn imon isump vsen r 3 modulator current sense - + fb comp rtn e/a - + ? + + dac vw temp monitor vr_hot# ntc t_monitor prog2 prog1 imax vboot tmax droop # of phases for ps1 set (a/d) prog digital interface alert# sda a/d vready d/a vr_on prog t_monitor imon dac vdd vin phase current balance pwm3 droop ovp addr power-on reset (por) ibal fb2 sclk vset1 vset2 psi
ISL6353 4 september 15, 2011 fn6897.0 pin configuration ISL6353 (40 ld tqfn) top view 1 40 2 3 4 5 6 7 8 9 10 30 29 28 27 26 25 24 23 22 21 39 38 37 36 35 34 33 32 31 11 12 13 14 15 16 17 18 19 20 addr ovp vset1 vset2 psi prog2 boot2 ug2 ph2 gnd lg2 vddp pwm3 lg1 gnd ph1 ug1 boot1 prog1 vin sda alert# sclk vr_on pgood imon vr_hot# ntc vw comp fb fb2 isen3 isen2 isen1 rtn isumn isump vdd vsen gnd (bottom pad) pin descriptions pin number symbol description 1, 2, 3 sda, alert#, sclk serial communication bus sign als connected between the cpu and the voltage regulator. 4 vr_on voltage regulator enable input. a high level logic signal on this pin enables the vr. 5 pgood open-drain output to indicate the regulator is ready to supply regulated voltage. use an appropriate external pull-up resistor. 6 imon output current monitor pin. imon sources a current pr oportional to the regulator output current. a resistor connected from this pin to ground will set a voltage that is proportional to the load current. this voltage is sampled with an internal adc to produce a digital imon signal that can be read through the serial communications bus. 7 vr_hot# thermal overload output indicator. 8 ntc thermistor input to the vr_hot# circuit. 9 vw window voltage set pin used to set the switching freque ncy. a resistor from this pin to comp programs the switching frequency (18k gives approximately 300khz). 10 comp this pin is the output of the error amplifier. 11 fb this pin is the inverting input of the error amplifier. 12 fb2 this pin switches in an rc network from vout to fb in ps1 and ps2 modes to help improve transient performance and phase margin when dropping phases in low power st ates. there is a switch between the fb2 pin and the fb pin. the switch is off in the ps0 state and on in the ps1 and ps2 states. if this function is not needed, the pin can be left open. 13 isen3 individual current sensing input for phase 3. leave th is pin open when ISL6353 is configured in 2-phase mode. 14 isen2 individual current sensing input for phase 2. when isen2 is pulled to 5v vdd, the controller will disable phase 2, and the controller will run in 1-phase mode. 15 isen1 individual current sensing input for phase 1. 16 vsen output voltage sense pin. connect to the output volt age (typically vddq) at the de sired remote voltage sensing location.
ISL6353 5 september 15, 2011 fn6897.0 17 rtn output voltage sense return pin. connect to the ground at desired remote sensing location. 18, 19 isumn and isump inverting and non-inverting input of th e transconductance amplifier for current monitoring and ocp. 20 vdd 5v bias power. 21 vin input supply voltage, used for input supply feed-forward compensation. 22 prog1 the program pin for the voltage regulator i max setting. refer to table 6. 23 boot1 connect an mlcc capacitor across the boot1 and the ph 1 pins. the boot capacitor is charged through an internal switch connected from the vddp pin to the boot1 pin. 24 ug1 output of the phase 1 high-side mosfet gate driver. connect the ug1 pin to the gate of the phase 1 high-side mosfet. 25 ph1 current return path for the phase 1 high-side mosfet ga te driver. connect the ph1 pin to the node consisting of the high-side mosfet source, the low-side mosfet drain, and the output inductor of phase 1. 26 gnd this is an electrical ground connection for the ic. connec t this pin to the ground plane of the pcb right next to the controller or to the exposed pad on the back of the ic using a low impedance path. 27 lg1 output of the phase 1 low-side mosfet gate driver. connect the lg1 pin to the gate of the phase 1 low-side mosfet. 28 pwm3 pwm output for phase 3. when pwm3 is pulled to 5v vdd, the controller will disable phase 3 and allow other phases to operate. 29 vddp input voltage bias for the internal gate drivers. connec t +5v to the vddp pin. decouple with at least 1f using an mlcc capacitor to the ground plane close to the ic. 30 lg2 output of the phase 2 low-side mosfet gate driver. connect the lg2 pin to the gate of the phase 2 low-side mosfet. 31 gnd this is an electrical ground connection for the ic. connec t this pin to the ground plane of the pcb right next to the controller or to the exposed pad on the back of the ic using a low impedance path. 32 ph2 current return path for the phase 2 high-side mosfet ga te driver. connect the ph2 pin to the node consisting of the high-side mosfet source, the low-side mosfet drain, and the output inductor of phase 2. 33 ug2 output of the phase 2 high-side mosfet gate driver. connect the ug2 pin to the gate of the phase 2 high-side mosfet. 34 boot2 connect an mlcc capacitor across the boot2 and the ph 2 pins. the boot capacitor is charged through an internal switch connected from the vddp pin to the boot2 pin. 35 prog2 the program pin for the voltage regulator v boot voltage, droop enable/disable an d the number of active phases for ps1 mode. 36 psi this pin can be used to set the power state of the contro ller with external logic signals. by connecting this pin to ground, the controller will refer only to the power state indicated by the serial communication bus register. if the pin is connected to a high impedance, the controller will ente r the ps1 state. if the pin is connected to a logic high, the controller will enter the ps2 state. 37 vset2 this pin is a logic input that can be used in conjunction with vset1 to pr ogram the output voltage of the regulator with external logic signals. refer to table 9. by connecti ng vset1 and vset2 to ground, the controller will refer to the vid setting indicated by the serial communication bus register. 38 vset1 this pin is a logic input that can be used in conjunction with vset2 to pr ogram the output voltage of the regulator with external signals. refer to table 9. by connecting vs et1 and vset2 to ground, the controller will refer to the vid setting indicated by the seri al communication bus register. 39 ovp an inverter output, latched high for an overvoltage event. it is reset by por. 40 addr this pin sets the address offset register, range from 0 to 13 (0h to dh). - gnd (bottom pad) electrical ground of the ic. unless otherwise stated, all signals are referenced to the gnd pin. connect this ground pad to the ground plane through a low impedance path. re commend use of at least 5 vias to connect to ground planes in pcb internal layers. pin descriptions (continued) pin number symbol description
ISL6353 6 september 15, 2011 fn6897.0 ordering information part number (notes 1, 2, 3) part marking temp. range (c) package (pb-free) pkg. dwg. # ISL6353crtz ISL6353 crtz 0 to +70 40 ld 5x5 tqfn l40.5x5 ISL6353irtz ISL6353 irtz -40 to +85 40 ld 5x5 tqfn l40.5x5 ISL6353eval1z evaluation board notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. intersil pb-free plus anneal products employ special pb-free material sets; molding compounds/die attach materials and 100% m atte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free p roducts are msl classified at pb-free peak reflow temp eratures that meet or exceed the pb-fr ee requirements of ipc/jedec j std-020. 3. for moisture sensitivity level (msl), please see device information page for ISL6353 . for more information on msl please see techbrief tb363 .
ISL6353 7 september 15, 2011 fn6897.0 table of contents simplified application circuit using inductor dcr current sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 recommended operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 gate driver timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 theory of operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 multiphase r3 modulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 diode emulation and period stretching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 start-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 voltage regulation and differential sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 vid table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 vid offset table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 inductor dcr current-sensing network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 resistor current-sensing network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 current monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 phase current balancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 ccm switching frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 phase count configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 dynamic operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 protection functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 fb2 function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 adaptive body diode conduction time reduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 system parameter programming prog1/2 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 svid address setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 external control of vout and power state vset1/2, psi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 supported serial vid data and configuration registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 package outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
ISL6353 8 september 15, 2011 fn6897.0 absolute maximum rating s thermal information supply voltage, vdd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +7v input supply voltage, vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +28v boot voltage (boot) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +33v boot to phase voltage (boot-phase) . . . . . . . . . . . . . . . . -0.3v to +7v(dc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +9v(<10ns) phase voltage (phase) . . . . . . . . . . . . . . . . -7v (<20ns pulse width, 10j) ugate voltage (ugate) . . . . . . . . . . . . . . . . . . . phase - 0.3v (dc) to boot . . . . . . . . . . . . . . . . . . . . . . . phase-5v (<20ns pulse width, 10j) to boot lgate voltage (lgate). . . . . . . . . . . . . . . . . . . . . . -0.3v (dc) to vdd + 0.3v . . . . . . . . . . . . . . . . . . . . . . . -2.5v (<20ns pulse width, 5j) to vdd + 0.3v all other pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to (vdd +0.3v) open drain outputs, pgood, vr_hot#, alert#. . . . . . . . . . -0.3v to +7v esd rating human body model (tested per jesd22-a114e) . . . . . . . . . . . . . . 2000v machine model (tested per jesd22-a115-a) . . . . . . . . . . . . . . . . . 200v charged device model (tested per jesd22-c101a) . . . . . . . . . . . 750v latch up (tested per jesd-78b; class 2, level a) . . . . . . . . . . . . . . 100ma thermal resistance (typical) ja (c/w) jc (c/w) 40 ld tqfn package (notes 4, 5) . . . . . . . 32 3 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150c maximum storage temperature range . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp recommended operating conditions supply voltage, vdd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5v 5% input voltage, vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5v to 25v ambient temperature ISL6353crtz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0c to +70c ISL6353irtz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c junction temperature ISL6353crtz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0c to +125c ISL6353irtz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +125c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 . 5. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. electrical specifications operating conditions: v dd = 5v, t a = 0c to +70c for ISL6353crtz and t a = -40c to +85c for ISL6353irtz, f sw = 300khz, unless otherwise noted. boldface limits apply over the operating temperature range. parameter symbol test conditions min (note 6) typ max (note 6) units input power supply +5v supply current i vdd vr_on = 1v 4 4.6 ma vr_on = 0v 1 a input supply current i vin vr_on = 0v 1 a power-on-reset threshold por r v dd rising 4.35 4.5 v por f v dd falling 4.00 4.15 v por r vin pin rising 4.00 4.35 v por f vin pin falling 2.8 3.50 v system and references system accuracy crtz %error (v cc_core ) no load; closed loop, active mode range vid = 0.75v to 1.50v, -0.5 +0.5 % vid = 0.5v to 0.7375v -8 8 mv vid = 0.3v to 0.4875v -15 15 mv irtz %error (v cc_core ) no load; closed loop, active mode range vid = 0.75v to 1.50v, -0.8 0.8 % vid = 0.5v to 0.7375v -10 10 mv vid = 0.3v to 0.4875v -18 18 mv maximum output voltage + offset v cc_core(max) vid = ffh offset = 7fh 1.520+ 0.635 = 2.155 v minimum output voltage v cc_core(min) vid = 01h offset = 00h 0.25 v
ISL6353 9 september 15, 2011 fn6897.0 channel frequency nominal channel frequency f sw(nom) r fset = 18k ? , 3-channel operation, v comp = 1v 280 300 320 khz adjustment range 200 500 khz amplifiers current-sense amplifier input offset i fb = 0a -0.1 +0.1 mv error amp dc gain a v0 119 db error amp gain-bandwidth product gbw c l = 20pf 17 mhz isen1/2/3 input bias current 20 na power good and protection monitors pgood low voltage v ol i pgood = 4ma 0.26 0.4 v pgood leakage current i oh pgood = 3.3v -1 1 a alert# pull-down resistance 7 13 ? alert# leakage current 1 a vr_hot# pull-down resistance 7 13 ? vr_hot# leakage current 1 a gate driver ugate pull-up resistance r ugpu 200ma source current 1.0 1.5 ? ugate source current i ugsrc ugate - phase = 2.5v 2.0 a ugate sink resistance r ugpd 250ma sink current 1.0 1.5 ? ugate sink current i ugsnk ugate - phase = 2.5v 2.0 a lgate pull-up resistance r lgpu 250ma source current 1.0 1.5 ? lgate source current i lgsrc lgate - gnd = 2.5v 2.0 a lgate sink resistance r lgpd 250ma sink current 0.5 0.9 ? lgate sink current i lgsnk lgate - gnd = 2.5v 4.0 a ugate to lgate deadtime t ugflgr ugate falling to lgate rising, no load 23 ns lgate to ugate deadtime t lgfugr lgate falling to ugate rising, no load 28 ns protection functions pre-charge overvoltage threshold ov p vsen rising above setpoint for >1ms 2.29 2.35 v overvoltage threshold ov h vsen rising above setpoint for >1ms 145 175 200 mv ovp pin sink current i ovp v ovp = vdd - 1v 20 ma overcurrent threshold crtz 3/2/1-phase config, ps0 56.5 60 64.5 a irtz 3/2/1-phase config, ps0 54.5 60 64.5 a crtz 3-phase config, ps1 - drop to 2-phase 38.3 40 43.2 a irtz 3-phase config, ps1 - drop to 2-phase 37 40 43.2 a crtz 3-phase config, ps1/2 - drop to 1-phase 19 20 22.25 a irtz 3-phase config, ps1/2 - drop to 1-phase 18.5 20 22.25 a crtz 2-phase config, ps1/2 - drop to 1-phase 28 30 33 a irtz 2-phase config, ps1/2 - drop to 1-phase 27 30 33 a electrical specifications operating conditions: v dd = 5v, t a = 0c to +70c for ISL6353crtz and t a = -40c to +85c for ISL6353irtz, f sw = 300khz, unless otherwise noted. boldface limits apply over the operating temperature range. (continued) parameter symbol test conditions min (note 6) typ max (note 6) units
ISL6353 10 september 15, 2011 fn6897.0 way overcurrent threshold crtz 3/2/1-phase config, ps0 76.8 88 100 a irtz 3/2/1-phase config, ps0 74 88 100 a crtz 3-phase config, ps1 - drop to 2-phase 52 60 68 a irtz 3-phase config, ps1 - drop to 2-phase 50 60 68 a crtz 3-phase config, ps1/2 - drop to 1-phase 28 32 35.8 a irtz 3-phase config, ps1/2 - drop to 1-phase 27 32 35.8 a crtz 2-phase config, ps1/2 - drop to 1-phase 40 46 52 a irtz 2-phase config, ps1/2 - drop to 1-phase 39.5 46 52 a current imbalance threshold one isen above another isen for >1.2ms 20 mv pwm pwm3 output low v ol_max sinking 5ma 1.0 v pwm3 output high v oh_min sourcing 5ma 3.5 v pwm3 tri-state leakage pwm3 = 2.5v 2 a thermal monitor ntc source current crtz ntc = 1.3v 58 60 62 a irtz ntc = 1.3v 56 60 62 a vr_hot# trip voltage falling 0.895 0.91 v vr_hot# reset voltage rising 0.95 0.965 v alert# trip voltage falling 0.915 0.93 v alert# reset voltage rising 0.97 0.985 v current monitor imon output current i imon isum- pin current = 50a 12.3 12.45 12.6 a isum- pin current = 2a 400 500 600 na iccmax alert trip voltage v imonmax rising 1.2 1.225 v iccmax alert reset voltage falling 1.05 1.14 v inputs vr_on input low v il_max 0.3 v vr_on input high v ih_min 0.8 v vr_on leakage current i vr_on vr_on = 0v -1 0a vr_on = 1v, 300k ? typical pull-down 3.3 a vset1/2 input low vset il_max 1.5 v vset1/2 input high vset ih_min 3.1 v psi sink/source current psi voltage 12 16 20 a psi pin state ps0, v dd =5v 00.51 v ps1, v dd =5v 1.06 3.91 v ps2, v dd =5v 4.47 5 v psi high-z voltage 2.12 2.37 2.60 v sclk, sda sclk, sda leakage vr_on = 0v, sclk & sda = 0v & 1v -1 1 a vr_on = 1v, sclk & sda = 1v -5 1 a vr_on = 1v, sda = 0v 20 a vr_on = 1v, sclk = 0v 40 a note: 6. compliance to datasheet limits is assu red by one or more methods: production test, characterization and/or design. electrical specifications operating conditions: v dd = 5v, t a = 0c to +70c for ISL6353crtz and t a = -40c to +85c for ISL6353irtz, f sw = 300khz, unless otherwise noted. boldface limits apply over the operating temperature range. (continued) parameter symbol test conditions min (note 6) typ max (note 6) units
ISL6353 11 september 15, 2011 fn6897.0 gate driver timing diagram theory of operation multiphase r 3 modulator pwm ugate lgate 1v 1v t ugflgr t rl t fu t ru t fl t lgfugr figure 3. r 3 modulator circuit crm gmvo master clock vw comp master clock phase sequencer clock1 clock2 r i l1 gm clock1 phase1 crs1 vw s q pwm1 l1 r i l2 gm clock2 phase2 crs2 vw s q pwm2 l2 co vo vcrm vcrs1 vcrs2 master clock circuit slave circuit 1 slave circuit 2 r i l3 gm clock3 phase3 crs3 vw s q pwm3 l3 vcrs3 slave circuit 3 clock3 figure 4. r 3 modulator operation principles in steady state comp v crm master clock pwm1 vw clock1 pwm2 clock2 hysteretic window pwm3 v crs3 clock3 v crs2 v crs1 vw
ISL6353 12 september 15, 2011 fn6897.0 the ISL6353 is a multiphase re gulator controller implementing the intel vr12? protocol primar ily intended for use in ddr memory regulator applications. it can be programmed for 1-, 2- or 3-phase operation. it uses intersil?s patented r 3 (robust ripple regulator?) modulator. the r 3 modulator combines the best features of fixed frequency pwm and hysteretic pwm while eliminating many of their resp ective shortcomings. figure 3 conceptually shows the ISL6353 multiphase r 3 modulator circuit, and figure 4 shows the principle of operation. a current source flows from the vw pin to the comp pin, creating a voltage window set by the resistor between the two pins. this voltage window is called the vw window in the following discussion. inside the ic, the modulator uses the master clock circuit to generate the clocks for the slave circuits. the modulator discharges the ripple capacitor c rm with a current source equal to g m v o , where g m is a gain factor. the c rm voltage v crm is a sawtooth waveform traversing between the vw and comp voltages. it resets to vw when it hits comp, and generates a one-shot master clock signal. a phase sequencer distributes the ma ster clock signal to the slave circuits. if the ISL6353 is in 3-ph ase mode, the master clock signal will be distributed to the three phases, and the clock1~3 signals will be 120 out-of-phase. if the ISL6353 is in 2-phase mode, the master clock signal will be distributed to phases 1 and 2, and the clock1 and clock2 signals will be 180 out-of-phase. if the ISL6353 is in 1-phase mode, the master clock signal will be distributed to phase 1 only and is the clock1 signal. each slave circuit has its own ripple capacitor c rs , whose voltage mimics the inductor ripple current. a g m amplifier converts the inductor voltage into a current source to charge and discharge c rs . the slave circuit turns on its pwm pulse upon receiving the clock signal, and the current source charges c rs . when c rs voltage v crs hits vw, the slave circuit turns off the pwm pulse, and the current source discharges c rs . since the ISL6353 individual phase modulators use a large-amplitude and noise-free synthesized signal, v crs , to determine the pulse width, phase jitter is lower than conventional hysteretic mode and fixed pwm mode controllers. unlike conventional hysteretic mode converters, the ISL6353 has an error amplifier that allows the controller to maintain 0.5% output voltage accuracy. figure 5 shows the principle of operation during a load step-up response. the comp voltage rises after the load step up, generating master clock pulses more quickly, so pwm pulses turn on earlier, increasing the effective switching frequency. this allows for higher control loop ba ndwidth than conventional fixed frequency pwm controllers. the vw voltage rises as the comp voltage rises, making the pwm pulses wider as well. during load step-down response, comp voltag e falls. it takes the master clock circuit longer to generate the next clock signal, so the pwm pulse is held off until needed. the vw voltage falls as the comp voltage falls, reducing the curren t pwm pulse width. this kind of behavior gives the ISL6353 exce llent load transient response. the fact that all the phases share the same vw window voltage also ensures excellent dynamic current balance among phases. diode emulation and period stretching ISL6353 can operate in diode emulation (de) mode to improve light load efficiency. in de mode , the low-side mosfet conducts when the current is flowing from source to drain and does not allow reverse current, thus emulat ing a diode. as figure 6 shows, when lgate is on, the low-side mo sfet carries current, creating negative voltage on the phase node due to the voltage drop across the on-resistance. the ISL6353 monitors the current by monitoring the phase node voltag e. it turns off lgate when the phase node voltage reaches zero to prevent the inductor current from reversing direction and cr eating unnecessary power loss. if the load current is light enough , as figure 6 shows, the inductor current will reach and stay at ze ro before the next phase node pulse, and the regulator is in discontinuous conduction mode (dcm). if the load current is heavy enough, the inductor current will never reach 0a, and the regulator is in ccm although the controller is in de mode. figure 5. r 3 modulator operation during a load step-up response comp vcrm master clock pwm1 vcrs1 vw clock1 pwm2 vcrs2 clock2 pwm3 clock3 vcrs3 vw figure 6. diode emulation operation ugate phase il lgate
ISL6353 13 september 15, 2011 fn6897.0 figure 7 shows the principle of op eration in diode emulation mode at light load. the load gets increm entally lighter in the three cases from top to bottom. the pwm on-time is determined by the vw window size and therefore it is the same, making the inductor current triangle the same in the three cases. the ISL6353 clamps the ripple capacitor voltage v crs in de mode to make it mimic the inductor current. it takes the comp voltage longer to hit v crs , naturally stretching the switching period. the inductor current triangles move further apart from each other such that the inductor current average value is equal to the load current. the reduced switching frequency helps increase light load efficiency. start-up timing with the controller's v dd voltage above the por threshold, the start-up sequence begins abou t 1.3ms after vr_on exceeds the logic high threshold. the ISL6353 uses digital soft-start to ramp up the dac to the boot voltage, v boot . v boot is set by the prog2 pin resistor and the status of the vset1/2 pins. the dac slew rate during soft-start is about 2.5mv/s. pgood is asserted high at the end of the start-up sequence indicating that the output voltage has moved to the v boot setting, the vr is operating properly and all phases are switch ing. figure 8 shows the typical start-up timing. voltage regulation and differential sensing after the start sequence, the isl6 353 regulates the output voltage to the value set by the setvid commands through the svid bus or to the value set by the status of the vset1/2 pins. the ISL6353 will regulate the output voltage to vid + offset (register 33h). a differential amplifier allows remote voltage sensing for precise voltage regulation. vid table the ISL6353 will regulate the output voltage to vid+offset (33h). table 1 shows the output voltage setting based on the vid register setting. figure 7. period stretching i l i l v crs il v crs v crs vw ccm/dcm boundary light dcm deep dcm vw vw table 1. vid table vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 hex v o (v) 0 0 0 0 0 0 0 0 0 0 0.0000 0 0 0 0 0 0 0 1 0 1 0.2500 0 0 0 0 0 0 1 0 0 2 0.2550 0 0 0 0 0 0 1 1 0 3 0.2600 0 0 0 0 0 1 0 0 0 4 0.2650 00000101050.2700 00000110060.2750 0 0 0 0 0 1 1 1 0 7 0.2800 0 0 0 0 1 0 0 0 0 8 0.2850 0 0 0 0 1 0 0 1 0 9 0.2900 0 0 0 0 1 0 1 0 0 a 0.2950 0 0 0 0 1 0 1 1 0 b 0.3000 0 0 0 0 1 1 0 0 0 c 0.3050 000011010d0.3100 000011100e0.3150 0 0 0 0 1 1 1 1 0 f 0.3200 0 0 0 1 0 0 0 0 1 0 0.3250 0 0 0 1 0 0 0 1 1 1 0.3300 0 0 0 1 0 0 1 0 1 2 0.3350 0 0 0 1 0 0 1 1 1 3 0.3400 0 0 0 1 0 1 0 0 1 4 0.3450 0 0 0 1 0 1 0 1 1 5 0.3500 figure 8. soft-start waveforms vdd vr_on dac 1.3ms 2.5mv/s vboot pgood ready for svid command
ISL6353 14 september 15, 2011 fn6897.0 00010110160. 3550 00010111170. 3600 00011000180. 3650 00011001190.3700 000110101a0.3750 000110111b0. 3800 000111001c0. 3850 000111011d0. 3900 000111101e0. 3950 000111111f0. 4000 00100000200. 4050 00100001210.4100 00100010220.4150 00100011230. 4200 00100100240. 4250 00100101250. 4300 00100110260. 4350 00100111270. 4400 00101000280. 4450 00101001290. 4500 001010102a0. 4550 001010112b0. 4600 001011002c0. 4650 001011012d0.4700 001011102e0.4750 001011112f0. 4800 00110000300. 4850 00110001310. 4900 00110010320. 4950 00110011330. 5000 00110100340. 5050 00110101350.5100 00110110360.5150 00110111370. 5200 00111000380. 5250 00111001390. 5300 001110103a0. 5350 001110113b0.5400 001111003c0.5450 001111013d0. 5500 001111103e0. 5550 001111113f0. 5600 table 1. vid table (continued) vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 hex v o (v) 0 1 0 0 0 0 0 0 4 0 0.5650 01000001410.5700 01000010420.5750 0 1 0 0 0 0 1 1 4 3 0.5800 0 1 0 0 0 1 0 0 4 4 0.5850 0 1 0 0 0 1 0 1 4 5 0.5900 0 1 0 0 0 1 1 0 4 6 0.5950 0 1 0 0 0 1 1 1 4 7 0.6000 0 1 0 0 1 0 0 0 4 8 0.6050 01001001490.6100 010010104a0.6150 0 1 0 0 1 0 1 1 4 b 0.6200 0 1 0 0 1 1 0 0 4 c 0.6250 0 1 0 0 1 1 0 1 4 d 0.6300 0 1 0 0 1 1 1 0 4 e 0.6350 0 1 0 0 1 1 1 1 4 f 0.6400 0 1 0 1 0 0 0 0 5 0 0.6450 0 1 0 1 0 0 0 1 5 1 0.6500 0 1 0 1 0 0 1 0 5 2 0.6550 0 1 0 1 0 0 1 1 5 3 0.6600 0 1 0 1 0 1 0 0 5 4 0.6650 0 1 0 1 0 1 0 1 5 5 0.6700 0 1 0 1 0 1 1 0 5 6 0.6750 0 1 0 1 0 1 1 1 5 7 0.6800 0 1 0 1 1 0 0 0 5 8 0.6850 0 1 0 1 1 0 0 1 5 9 0.6900 0 1 0 1 1 0 1 0 5 a 0.6950 0 1 0 1 1 0 1 1 5 b 0.7000 0 1 0 1 1 1 0 0 5 c 0.7050 010111015d0.7100 010111105e0.7150 0 1 0 1 1 1 1 1 5 f 0.7200 0 1 1 0 0 0 0 0 6 0 0.7250 0 1 1 0 0 0 0 1 6 1 0.7300 0 1 1 0 0 0 1 0 6 2 0.7350 01100011630.7400 01100100640.7450 0 1 1 0 0 1 0 1 6 5 0.7500 0 1 1 0 0 1 1 0 6 6 0.7550 01100111670.7600 01101000680.7650 01101001690.7700 table 1. vid table (continued) vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 hex v o (v)
ISL6353 15 september 15, 2011 fn6897.0 011010106a0.7750 011010116b0. 7800 011011006c0. 7850 011011016d0. 7900 011011106e0. 7950 011011116f0. 8000 01110000700. 8050 01110001710.8100 01110010720.8150 01110011730. 8200 01110100740. 8250 01110101750. 8300 01110110760. 8350 01110111770. 8400 01111000780. 8450 01111001790. 8500 011110107a0. 8550 011110117b0. 8600 011111007c0. 8650 011111017d0.8700 011111107e0.8750 011111117f0. 8800 10000000800. 8850 10000001810. 8900 10000010820. 8950 10000011830. 9000 10000100840. 9050 10000101850.9100 10000110860.9150 10000111870. 9200 10001000880. 9250 10001001890. 9300 100010108a0. 9350 100010118b0. 9400 100011008c0. 9450 100011018d0. 9500 100011108e0. 9550 100011118f0. 9600 10010000900. 9650 10010001910.9700 10010010920.9750 10010011930. 9800 table 1. vid table (continued) vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 hex v o (v) 1 0 0 1 0 1 0 0 9 4 0.9850 1 0 0 1 0 1 0 1 9 5 0.9900 1 0 0 1 0 1 1 0 9 6 0.9950 10010111971.0000 10011000981.0050 10011001991.0100 100110109a1.0150 100110119b1.0200 100111009c1.0250 100111019d1.0300 100111109e1.0350 100111119f1.0400 10100000a01.0450 10100001a11.0500 10100010a21.0550 10100011a31.0600 10100100a41.0650 10100101a51.0700 10100110a61.0750 10100111a71.0800 10101000a81.0850 10101001a91.0900 10101010aa1.0950 10101011ab1.1000 10101100ac1.1050 10101101ad1.1100 10101110ae1.1150 10101111af1.1200 10110000b01.1250 10110001b11.1300 10110010b21.1350 10110011b31.1400 10110100b41.1450 10110101b51.1500 10110110b61.1550 10110111b71.1600 10111000b81.1650 10111001b91.1700 10111010ba1.1750 10111011bb1.1800 10111100bc1.1850 10111101bd1.1900 table 1. vid table (continued) vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 hex v o (v)
ISL6353 16 september 15, 2011 fn6897.0 vid offset table the ISL6353 will regulate the output voltage to vid+offset (33h). table 2 shows the output voltage setting based on the vid register setting. 10111110be1. 1950 10111111bf1.2000 11000000c01.2050 11000001c11.2100 11000010c21.2150 11000011c31.2200 11000100c41.2250 11000101c51.2300 11000110c61.2350 11000111c71.2400 11001000c81.2450 11001001c91.2500 11001010ca1.2550 11001011cb1.2600 11001100cc1.2650 11001101cd1.2700 11001110ce1.2750 11001111cf1.2800 11010000d01.2850 11010001d11.2900 11010010d21.2950 11010011d31.3000 11010100d41.3050 11010101d51.3100 11010110d61.3150 11010111d71.3200 11011000d81.3250 11011001d91.3300 11011010da1.3350 11011011db1.3400 11011100dc1.3450 11011101dd1.3500 11011110de1.3550 11011111df1.3600 11100000e01.3650 11100001e11.3700 11100010e21.3750 11100011e31.3800 11100100e41.3850 11100101e51.3900 11100110e61.3950 11100111e71.4000 table 1. vid table (continued) vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 hex v o (v) 11101000e81.4050 11101001e91.4100 11101010ea1.4150 11101011eb1.4200 11101100ec1.4250 11101101ed1.4300 11101110ee1.4350 11101111ef1.4400 11110000f01.4450 11110001f11.4500 11110010f21.4550 11110011f31.4600 11110100f41.4650 11110101f51.4700 11110110f61.4750 11110111f71.4800 11111000f81.4850 11111001f91.4900 11111010fa1.4950 11111011fb1.5000 11111100fc1.5050 11111101fd1.5100 11111110fe1.5150 11111111ff1.5200 table 2. vid table ofs7 ofs6 ofs5 ofs4 ofs3 ofs2 ofs1 ofs0 hex v ofs (v) 0 0 0 0 0 0 0 0 0 0 0.0000 00000001010.005 00000010020.010 00000011030.015 00000100040.020 00000101050.025 00000110060.030 00000111070.035 00001000080.040 00001001090.045 000010100a0.050 table 1. vid table (continued) vid7 vid6 vid5 vid4 vid3 vid2 vid1 vid0 hex v o (v)
ISL6353 17 september 15, 2011 fn6897.0 000010110b0.055 000011000c0.060 000011010d0.065 000011100e0.070 000011110f0.075 00010000100.080 00010001110.085 00010010120.090 00010011130.095 00010100140.100 00010101150.105 00010110160.110 00010111170.115 00011000180.120 00011001190.125 000110101a0.130 000110111b0.135 000111001c0.140 000111011d0.145 000111101e0.150 000111111f0.155 00100000200.160 00100001210.165 00100010220.170 00100011230.175 00100100240.180 00100101250.185 00100110260.190 00100111270.195 00101000280.200 00101001290.205 001010102a0.210 001010112b0.215 001011002c0.220 001011012d0.225 001011102e0.230 001011112f0.235 00110000300.240 00110001310.245 00110010320.250 00110011330.255 00110100340.260 table 2. vid table (continued) ofs7 ofs6 ofs5 ofs4 ofs3 ofs2 ofs1 ofs0 hex v ofs (v) 00110101350.265 00110110360.270 00110111370.275 00111000380.280 00111001390.285 001110103a0.290 001110113b0.295 001111003c0.300 001111013d0.305 001111103e0.310 001111113f0.315 01000000400.320 01000001410.325 01000010420.330 01000011430.335 01000100440.340 01000101450.345 01000110460.350 01000111470.355 01001000480.360 01001001490.365 010010104a0.370 010010114b0.375 010011004c0.380 010011014d0.385 010011104e0.390 010011114f0.395 01010000500.400 01010001510.405 01010010520.410 01010011530.415 01010100540.420 01010101550.425 01010110560.430 01010111570.435 01011000580.440 01011001590.445 010110105a0.450 010110115b0.455 010111005c0.460 010111015d0.465 010111105e0.470 table 2. vid table (continued) ofs7 ofs6 ofs5 ofs4 ofs3 ofs2 ofs1 ofs0 hex v ofs (v)
ISL6353 18 september 15, 2011 fn6897.0 figure 9 shows the differential voltage sensing scheme. vcc sense and vss sense are the remote voltage sensing signals from the ddr memory. a unity gain differential amplifier senses the vss sense voltage and adds it to the dac output. the error amplifier regulates the inverting and the non-inverting input voltages to be equal as shown in equation 1: rewriting equation 1 gives equation 2: the vcc sense and vss sense signals are routed from the memory socket. in most cases the remote sensing location will be on the pcb right next to one of the ddr memory sockets. if a remote sensing location is used on a module that passes through a socket then the feedback signals will be open circuit in the absence of the module. as shown in figure 9, a ?catch? resistor should be added in this case to feed the local vr output voltage back to the compensator, and another ?catch? resistor should be added to connect the local vr output ground to the rtn pin. these resistors, typically 10 ~100 , will provide voltage feedback if the system is powered up without any memory cards installed. inductor dcr current-sensing network the ISL6353 can sense the inductor current through the intrinsic dc resistance (dcr) of the inductors or through precision resistors in series with the inductors. with both current-sensing methods, the voltage across capacitor c n represents the total inductor current from all phases. an amplifier converts the c n voltage, v cn , into an internal current source, i sense , with the gain set by resistor r i shown in equation 3. 010111115f0.475 01100000600.480 01100001610.485 01100010620.490 01100011630.495 01100100640.500 01100101650.505 01100110660.510 01100111670.515 01101000680.520 01101001690.525 011010106a0.530 011010116b0.535 011011006c0.540 011011016d0.545 011011106e0.550 011011116f0.555 01110000700.560 01110001710.565 01110010720.570 01110011730.575 01110100740.580 01110101750.585 01110110760.590 01110111770.595 01111000780.600 01111001790.605 011110107a0.610 011110117b0.615 011111007c0.620 011111017d0.625 011111107e0.630 011111117f0.635 table 2. vid table (continued) ofs7 ofs6 ofs5 ofs4 ofs3 ofs2 ofs1 ofs0 hex v ofs (v) figure 9. differential sensing x 1 e/a vcc sense v dac vss sense + = (eq. 1) vcc sense vss sense ? v dac = (eq. 2) i sense v cn r i --------- = (eq. 3)
ISL6353 19 september 15, 2011 fn6897.0 the sensed current is used for cu rrent monitoring and overcurrent protection. figure 10 shows the inductor dcr current-sensing network for a 3-phase regulator. inductor current flows through the dcr and creates a voltage drop. each inductor has two resistors r sum and r o connected to the pads to accurately sense the inductor current by sensing the dcr voltage drop. the r sum and r o resistors are connected in a summing network as shown, and feed the total current information to the ntc network (consisting of r ntcs , r ntc and r p ) and capacitor c n . r ntc is a negative temperature coefficient (ntc) thermistor, used to compensate for the increase in inductor dcr as temperature increases. the inductor output pads are electrically shorted in the schematic, but have some parasitic impedance in the actual board layout, which is why the signals cannot simply be shorted together for the current-sense summing network. a resistor from 1 ~10 for r o is recommended to create quality signals. since the r o value is much smaller than the rest of the current sensing circuit, the following analysis will ignore it for simplicity. the summed inductor current information is represented at capacitor c n . equations 4 through 8 describe the frequency-domain relationship between total inductor current i o (s) and the c n voltage v cn (s): where n is the number of phases. transfer function a cs (s) always has unity gain at dc. the inductor dcr value increases as the wi nding temperature increases, giving higher a reading of the inductor dc current. the ntc r ntc values decreases as its temperatur e increases. proper selections of r sum , r ntcs , r p and r ntc parameters ensure that v cn represents the total inductor dc current over the temperature range of interest. there are many sets of parameters that can properly temperature- compensate the dcr change. since the ntc network and the r sum resistors form a voltage divider, v cn is always a fraction of the inductor dcr voltage. a higher ratio of v cn to the inductor dcr voltage is recommended so the current monitor and ocp circuit has a higher signal level to work with. a typical set of parameters that provide good temperature compensation are: r sum = 3.65k , r p =11k , r ntcs = 2.61k and r ntc = 10k (ert-j1vr103j). the ntc network component values may need to be fine tuned on actual boards. to help fine tune the network apply a full load condition to the regulator and record the imon pin voltage readin g immediately; then record the imon voltage reading again when the board has reached thermal steady state. a good ntc network can limit the imon voltage drift to within 1% over the temperature range. if droop is used for the ISL6353 based regulator the output voltage can be used for this test rather than imon. ddr memory regulators typically do not operate with droop enabled. the intersil evaluation board layout and current-sensing network parameters can be referred to in order to help minimize engineering time. v cn (s) needs to represent real-time i o (s) for the controller to achieve best ocp and imon resp onse. the transfer function a cs (s) has a pole sns and a zero l . l and sns should be matched so a cs (s) is unity gain at all frequencies. by forcing l equal to sns and solving for the solution, equation 9 gives cn value . for example, given n = 3, r sum = 3.65k , r p =11k , r ntcs =2.61k , r ntc = 10k , dcr = 0.29m and l = 0.22h, equation 9 gives c n = 0.79f. c n is the capacitor used to match the inductor time constant. sometimes it takes the parallel combination of two or more capacitors to get the desired value. to verify the capacitor value is correct a repetitive load can be placed on the output voltage and the imon voltage can be monitored. the capacitor in parallel with the imon resistor needs to be removed for this test. the figure 10. dcr current-sensing network cn rsum ro rntcs rntc rp dcr l dcr l rsum ro phase2 phase3 io dcr l phase1 ro rsum ri isum+ isum- vcn v cn s () r ntcnet r ntcnet r sum n -------------- + ----------------------------------------- dcr n ----------- - ?? ?? ?? ?? ?? i o s () a cs s () = (eq. 4) r ntcnet r ntcs r ntc + () r p r ntcs r ntc r p ++ -------------------------------------------------- - = (eq. 5) a cs s () 1 s l ------ + 1 s sns ------------ + ---------------------- = (eq. 6) l dcr l ----------- - = (eq. 7) sns 1 r ntcnet r sum n -------------- r ntcnet r sum n -------------- + ----------------------------------------- c n ------------------------------------------------------ = (eq. 8) c n l r ntcnet r sum n -------------- r ntcnet r sum n -------------- + ----------------------------------------- dcr ----------------------------------------------------------- - = (eq. 9)
ISL6353 20 september 15, 2011 fn6897.0 imon voltage should be approximat ely a square wave with little or no overshoot. in regulators without droop control the capacitor value can be selected to err on the high side to overdamp the current sense input to the controller to avoid overshoots. resistor current-sensing network figure 11 shows the precision re sistor current-sensing network for a 3-phase solution. each inductor has a series current-sensing resistor, r sen . r sum and r o are connected to the r sen pads to accurately capture the inductor current information. the r sum and r o resistors are connected to capacitor c n . r sum and c n form a filter for noise attenuation. equations 10 through 12 give v cn (s) expressions: transfer function a rsen (s) always has unity gain at dc. the current-sensing resistor r sen value will not have a significant variation over temperature, so there is no need for the ntc network. recommended values are r sum =1k and c n = 5600pf. overcurrent protection the ISL6353 implements overcurrent protection (ocp) by comparing the average value of the measured current i sense with an internal current source reference. the ocp threshold is 60a for 3-phase, 2-phase and 1-phase ps0 operation. in ps1/2 mode the ocp threshold is scaled ba sed on the number of active phases in ps1/2 mode divided by the number of active phases in ps0 mode. for example, if the regulator operates in 3-phase mode in ps0, 2-phase in ps1 mode and 1-phase in ps2 mode, the ocp threshold will be 60a in ps0 mode, 40a in ps1 mode and 20a in ps2 mode. for a 2- phase design, the ocp threshold is 60a in ps0 mode and 30a in ps1 and ps2 mode. the ISL6353 declares a ocp fault when i sense is above the threshold for 120s. referring to equation 3 and figure 10, resistor r i sets the sensed current i sense . in general, i sense can be set to 40a at the maximum load current expected in the design. the ocp trip level will be 1.5 times the maximum lo ad current with a threshold at 60a. the ocp ratio can be set to something other than 1.5 times the maximum load current by setting i sense = 60a/ocp ratio . for inductor dcr sensing, equation 13 gives the dc relationship of v cn (s) and i o (s). substitution of equation 13 into equation 3 gives equation 14: therefore : substitution of equation 5 and application of the full load condition in equation 15 gives equation 16: where i omax is the full load current, and i sensemax is the corresponding sensed current based on the desired ocp to i omax ratio. for resistor sensing, equation 17 gives the dc relationship of v cn (s) and i o (s). substitution of equation 17 into equation 3 gives equation 18: therefore: application of the full load condition gives equation 20: where i omax is the full load current, and i sensemax is the corresponding sensed current. figure 11. resistor current-sensing network cn rsum ro dcr l dcr l rsum ro phase2 phase3 io dcr l phase1 ro rsum ri isum+ isum- vcn rsen rsen rsen v cn s () r sen n ------------ i o s () a rsen s () = (eq. 10) a rsen s () 1 1 s sns ------------ + ---------------------- = (eq. 11) rsen 1 r sum n -------------- c n --------------------------- = (eq. 12) v cn r ntcnet r ntcnet r sum n -------------- + ----------------------------------------- dcr n ----------- - ?? ?? ?? ?? ?? i o = (eq. 13) i i sense 1 r i ---- - r ntcnet r ntcnet r sum n -------------- + ----------------------------------------- dcr n ----------- - i o = (eq. 14) r i r ntcnet dcr i o nr ntcnet r sum n -------------- + ?? ?? i sense ------------------------------------------------------------------------------- - = (eq. 15) r i r ntcs r ntc + () r p r ntcs r ntc r p ++ -------------------------------------------------- - dcr i omax n r ntcs r ntc + () r p r ntcs r ntc r p ++ -------------------------------------------------- - r sum n -------------- + ?? ?? ?? i sensemax ------------------------------------------------------------------------------------------------------------------------- - = (eq. 16) v cn r sen n ------------ i o = (eq. 17) i sense 1 r i ---- - r sen n ------------ i o = (eq. 18) r i r sen i o ni sense -------------------------- = (eq. 19) r i r sen i omax ni sensemax ------------------------------------- = (eq. 20)
ISL6353 21 september 15, 2011 fn6897.0 current monitor the ISL6353 provides a current monitor function. the imon pin outputs a high-speed analog current source that is 1/4 times the i sense current. a resistor r imon is connected to the imon pin to convert the imon pin current to a voltage. the voltage across r imon is expressed in equation 22: substitution of equation 14 into equation 22 gives equation 23: rewriting equation 23 gives equation 24 : substitution of equation 5 and application of the full load condition in equation 24 gives equation 25: where i omax is the full load current. a capacitor c imon can be paralleled with r imon to filter the imon pin voltage. the r imon c imon time constant is the user?s choice. the time constant should be long enough such that switching frequency ripple is removed. phase current balancing the ISL6353 monitors individual phase current by monitoring the isen1, isen2, and isen3 pin voltages. figure 12 shows the current balancing circuit reco mmended for the ISL6353. each phase node voltage is averaged by a low-pass filter consisting of r s and c s , and presented to the corresponding isen pin. a long time constant for r s c s should be used such that the isen voltages have minimal ripple and represent the dc current flowing through the inductors. recommended values are r s = 10k and c s =0.22f. r s should be routed to the inductor phase-node pad in order to help eliminate the effect of phase node parasitic pcb dcr. equations 26 through 28 give the isen pin voltages: where r dcr1 , r dcr2 and r dcr3 are inductor dcr; r pcb1 , r pcb2 and r pcb3 are parasitic pcb dcr between the inductor output pad and the output voltage rail; and i l1 , i l2 and i l3 are inductor average currents. the ISL6353 will adjust the phase pulse-width relative to the other phases to make v isen1 =v isen2 =v isen3 , thus to achieve i l1 =i l2 =i l3 , when r dcr1 =r dcr2 =r dcr3 and r pcb1 =r pcb2 =r pcb3 . using the same components for l1, l2 and l3 will provide a good match of r dcr1 , r dcr2 and r dcr3 . board layout will determine r pcb1 , r pcb2 and r pcb3 . each phase should be as symmetric as possible in the pcb layout for the power delivery path between each inductor and the output voltage load, such that r pcb1 =r pcb2 =r pcb3 . sometimes, it is difficult to implement a symmetric layout. for the circuit shown in figure 12, an asymmetric layout causes different r pcb1 , r pcb2 and r pcb3 resulting in phase current imbalance. figure 13 shows a differential-sensing current balancing circuit recommended for the ISL6353. the current sensing traces should be routed to the inductor pads so they only pick up the inductor dcr voltage. each isen pin sees the average voltage of three sources: its own phase inductor phase-node pad, i imon 1 4 --- i sense = (eq. 21) v rimon 1 4 -- - i sense r imon = (eq. 22) v rimon 1 4r i -------- - r ntcnet r ntcnet r sum n -------------- + ----------------------------------------- dcr n ----------- - i o r imon = (eq. 23) r imon v rimon r i nr ntcnet r sum + () 1 4 --- r ntcnet dcr i o ---------------------------------------------------------------------------------------- = (eq. 24) r imon v rimon r i n r ntcs r ntc + () r p r ntcs r ntc r p ++ -------------------------------------------------- - r sum + ?? ?? ?? 1 4 -- - r ntcs r ntc + () r p r ntcs r ntc r p ++ ------------------------------------------------------ - dcr i omax ----------------------------------------------------------------------------------------------------------------------- - = (eq. 25) figure 12. current balancing circuit internal to ic v o isen3 l3 rs cs isen2 rs cs isen1 rs cs l2 l1 rdcr3 rdcr2 rdcr1 phase3 phase2 phase1 il3 il2 il1 rpcb3 rpcb2 rpcb1 v isen1 r dcr1 r pcb1 + () i l1 = (eq. 26) v isen2 r dcr2 r pcb2 + () i l2 = (eq. 27) v isen3 r dcr3 r pcb3 + () i l3 = (eq. 28) figure 13. differential-sensing current balancing circuit internal to ic v o isen3 l3 rs cs isen2 rs cs isen1 rs cs l2 l1 rdcr3 rdcr2 rdcr1 phase3 phase2 phase1 il3 il2 il1 rpcb3 rpcb2 rpcb1 rs rs rs rs rs rs v3p v3n v2p v2n v1p v1n
ISL6353 22 september 15, 2011 fn6897.0 and the other two phases inductor output pads. equations 29 through 31 give the isen pin voltages: the ISL6353 will make v isen1 = v isen2 = v isen3 as in equations 32 and 33: rewriting equation 32 gives equation 34: and rewriting equation 33 gives equation 35: combining equations 34 and 35 gives equation 36: therefore: current balancing (i l1 =i l2 =i l3 ) is achieved when r dcr1 =r dcr2 =r dcr3 . r pcb1 , r pcb2 and r pcb3 will not have any effect. since the slave ripple capacitor voltages mimic the inductor currents, the r 3 ? modulator can naturally achieve excellent current balancing during steady-state and dynamic operation. the inductor currents follow the load current dynamic change, with the output capacitors supplying the difference. the inductor currents can track the load current well at low rep rate, but cannot keep up when the rep rate gets into the hundred-khz range, where it is out of the control loop bandwidth. th e controller achieves excellent current balancing in all cases. ccm switching frequency the resistor connected between the comp pin and the vw pin sets the vw windows size, therefore setting the steady state pwm switching frequency. when the ISL6353 is in continuous conduction mode (ccm), the switching frequency is not absolutely constant due to the nature of the r 3 modulator. as explained in the ?multiphase r3 modulator? on page 11, the effective switching frequency will increase during load step-up and will decrease during load st ep-down to achieve fast transient response. on the other hand, the sw itching frequency is relatively constant at steady state. equation 38 gives an estimate of the frequency-setting resistor r fset value. 20k r fset gives approximately 300khz switching frequency. lower resistance yields higher switching frequency. phase count configurations the ISL6353 can be configured fo r 1, 2 or 3-phase operation. for 2-phase configuration, tie th e pwm3 pin to vdd. phase 1 and phase 2 pwm pulses are 180 out-of-phase. leave the isen3 pin open for 2-phase configuration. for 1-phase configuration, tie th e pwm3 and isen2 pins to vdd. in this configuration, only phas e 1 is active. the isen3, isen2, isen1, and fb2 pins are not used because there is no need for current balancing or the fb2 function. modes of operation table 3 shows the modes of operat ion for the various power states programmed using the setps command through the svid bus or by changing the state of the psi pi n. table 3 is used in conjunction with the status of the prog2 pin. refer to table 7 for the prog2 programming options. dynamic operation the controller responds to vid changes by slewing to the new voltage at a slew rate indicate d in the setvid command. there are three setvid slew rates setvid_fast, setvid_slew and setvid_decay. the setvid_fast command prompts the controller to enter ccm and to actively drive the output voltage to the new vid value at a minimum 10mv/s slew rate. the setvid_slow command prompts the controller to enter ccm and to actively drive the output voltage to the new vid value at a minimum 2.5mv/s slew rate. the setvid_decay command prompts the controller to enter de mode. the output voltage will decay down to the new vid value at a slew rate determined by the load. if the voltage decay rate is v isen1 v 1p v 2n v 3n ++ = (eq. 29) v isen2 v 1n v 2p v 3n ++ = (eq. 30) v isen3 v 1n v 2n v 3p ++ = (eq. 31) v 1p v 2n v 3n ++ v 1n v 2p v 3n ++ = (eq. 32) v 1n v 2p v 3n ++ v 1n v 2n v 3p ++ = (eq. 33) v 1p v 1n ? v 2p v 2n ? = (eq. 34) v 2p v 2n ? v 3p v 3n ? = (eq. 35) v 1p v 1n ? v 2p v 2n ? v 3p v 3n ? == (eq. 36) r dcr1 i l1 r dcr2 i l2 r dcr3 i l3 == (eq. 37) table 3. ISL6353 modes of operation configuration ps# operational mode 3-phase configuration ps0 3-phase ccm ps1 2-phase ccm or 1-phase ccm ps2 1-phase de ps3 1-phase de 2-phase configuration ps0 2-phase ccm ps1 1-phase ccm ps2 1-phase de ps3 1-phase de 1-phase configuration ps0 1-phase ccm ps1 1-phase ccm ps2 1-phase de ps3 1-phase de r fset () 1.293 10 7 ? f sw 2 0.1445 f sw 52055 + ? ? ?? = (eq. 38)
ISL6353 23 september 15, 2011 fn6897.0 too fast, the controller will limit the voltage slew rate at the setvid_slow slew rate. alert# will be asserted low at the end of setvid_fast and setvid_slow vid transitions. when the ISL6353 is in de mode, it will actively drive the output voltage up when the vid changes to a higher value. de operation will resume after reaching the new voltage level. if the load is light enough to warrant dcm, it will enter dcm after the inductor current has crossed zero for four consecutive cycles. the ISL6353 will remain in de mode when the vid changes to a lower value. the output voltage will decay to the new value and the load will determine the slew rate. protection functions the ISL6353 provides overcurrent, current-balance, overvoltage, and over-temperature protection. overcurrent protection the ISL6353 determines overcu rrent protection (ocp) by comparing the average value of the measured current i sense with an internal current source threshold. ISL6353 declares ocp when i sense is above the threshold for 120s. the way-overcurrent protection th reshold is significantly above the standard overcurrent protection threshold. the way-overcurrent function is intended to provide a fast overcurrent detection and action mechanism in a short circuit output condition. once the way-overcurrent condition is detected, the pwm outputs will immediately shut off and pgood will go low to maximize protection. current balance fault the ISL6353 monitors the isen pi n voltages to detect severe phase current imbalances. if any isen pin voltage is more than 20mv different than the averag e isen voltage for 1ms, the controller will declare a fault and latch off. overvoltage protection the ISL6353 will declare an ovp fault if the output voltage exceeds 175mv above the vid set value + positive offset. in the event of an ovp condition, the ovp pin is pulled high. ovp is blanked during dynamic vid events to prevent false trigger. during soft-start, the ovp threshold is set at 2.33v to avoid a false trigger due to turn on into a precharged output capacitor bank. power good indicator the ISL6353 takes the same action s for all of the above fault protection functions: pgood is set low and the high-side and low- side mosfets are turned off. an y residual inductor current will decay through the mosfet body diodes. these fault conditions can be reset by bringing vr _on low or by bringing v dd below the por threshold. when vr_on and v dd return to their high operating levels, a soft-start will occur. thermal monitor the ISL6353 has a thermal throttling feature. if the voltage on the ntc pin goes below the 0.91v threshold, the vr_hot# pin is pulled low indicating the need for thermal throttling to the system. the vr_hot# pin will be pulled back high if the voltage on the ntc pin goes above 0.95v. if the voltage on the ntc pin go es below 0.93v the alert# pin will be pulled low indicating a thermal alert. alert# is reset by checking the status register. alert# will be pulled low again if the ntc pin voltage goes above 0.97v. all the above fault conditions can be reset by bringing vr_on low or by bringing v dd below the por threshold. when vr_on and v dd return to their high operating levels, a soft-start will occur. vr_hot#/alert# behavior the controller drives a 60a current source out of the ntc pin. the current source flows through the ntc resistor network on the pin and creates a voltage that is monitored by the controller through an a/d converter (adc) to generate the tzone value. table 4 shows the typical programming table for tzone. the user needs to scale the ntc a networ k resistance such that it generates the ntc pin voltage that corresponds to the left-most column. table 4. tzone table vntc (v) tmax (%) tzone 0.86 >100 ffh 0.88 100 ffh 0.92 97 7fh 0.96 94 3fh 1.00 91 1fh 1.04 88 0fh 1.08 85 07h 1.12 82 03h 1.16 79 01h 1.20 76 01h >1.20 <76 00h 1 bit 6 =1 bit 7 =1 bit 5 =1 temp zone register 0001 1111 0011 1111 0 1 11 1111 1 111 1111 0 1 11 1111 0011 1111 0001 1111 status 1 register = ?001? = ?0 1 1? = ?0 0 1? temp zone 7 2 3 5 svid alert# vr_hot# 4 gerreg status1 8 6 9 10 11 1111 1111 0111 1111 0011 1111 0001 1111 12 13 15 gerreg status1 14 16 3% hysteris vr temperature figure 14. vr_hot#/alert# behavior
ISL6353 24 september 15, 2011 fn6897.0 figure 14 shows the how the ntc ne twork should be designed to get correct vr_hot#/alert# behavior when the system temperature rises and falls, manifested as the ntc pin voltage falling and rising. the series of events are: 1. the temperature rises so the ntc pin voltage drops. tzone value changes accordingly. 2. the temperature crosses the threshold where tzone register bit 6 changes from 0 to 1. 3. the controller changes status_1 register bit 1 from 0 to 1. 4. the controller asserts alert#. 5. the cpu reads status_1 register value to know that the alert assertion is due to tzone register bit 6 flipping. 6. the controller clears alert#. 7. the temperature continues rising. 8. the temperature crosses the threshold where tzone register bit 7 changes from 0 to 1. 9. the controllers asserts vr_hot# signal. the cpu throttles back and the system temperature starts dropping eventually. 10. the temperature crosses the threshold where tzone register bit 6 changes from 1 to 0. this threshold is 1 adc step lower than the one when vr_hot# gets asserted, to provide 3% hysteresis. 11. the controllers de-asserts vr_hot# signal. 12. the temperature crosses the threshold where tzone register bit 5 changes from 1 to 0. this threshold is 1 adc step lower than the one when alert# gets asserted during the temperature rise to provide 3% hysteresis. 13. the controller changes status_1 register bit 1 from 1 to 0. 14. the controller asserts alert#. 15. the cpu reads status_1 register value to know that the alert assertion is due to tzone register bit 5 flipping. 16. the controller clears alert#. table 5 summarizes the fault protection functionality. fb2 function figure 15 shows the fb2 function . in order to improve transient response and stability when phas es are disabled in ps1 or ps2 mode, the ISL6353 fb2 function allows a second type 3 compensation network to be connected from the output voltage to the fb pin. in ps0 mode of operation the fb2 sw itch is open (off). in ps1 or ps2 mode of operation the fb2 switch closes (on). the fb2 function ensures excellent transient response in both ps0 mode and ps1/2 mode. if th e fb2 function is not needed c2.2 and r3.2 can be unpopulated and the fb2 pin can be left unconnected. adaptive body diode conduction time reduction in dcm, the controller turns off the low-side mosfet when the inductor current approaches ze ro. during the on-time of the low-side mosfet, the phase voltage is negative and the amount is the mosfet r ds(on) voltage drop, which is proportional to the inductor current. a phase comp arator inside the controller monitors the phase voltage during on-time of the low-side mosfet and compares it with a threshold to determine the zero-crossing point of the inductor current. if the inductor current has not reached zero when the low- side mosfet turns off, it will flow through the low-side mosfet body diode, causing the phase node to have a larger voltage drop until it decays to zero. if the inductor current has crossed zero and reversed the direction when the low-side mosfet turns off, it will flow through the high-side mosfet body diode, causing the phase node to have a spike until the current decays to zero. the controller continues monitoring the phase voltage after turning off the low-side mosfet and adjusts the phase comparator threshold voltage accordingly in iterative steps such that the low-side mosfet body diode conducts for approximately 40ns to minimize the body diode-related loss. system parameter programming prog1/2 pins ISL6353 has two system parameter programming pins prog1 and prog2. some system parame ters, such as maximum output current, boot voltage, number of phases for ps1 state, can be programmed by changing the resistors connected to these three pins. table 5. fault protection summary fault type fault duration before protection protection action fault reset overcurrent 120s pwm tri-state, pgood latched low vr_on toggle or vdd toggle phase current unbalance 1ms way-overcurrent (1.5xoc) immediately overvoltage +175mv pgood latched low. actively pulls the output voltage to below vid value, then tri-state. figure 15. fb2 function in 2-phase mode r1 e/a r3.1 c2.1 c1 vref r2 c3 fb comp vsen controller in 3 or 2-phase mode c2.2 r3.2 fb2 r1 e/a r3.1 c2.1 c1 vref r2 c3 fb comp vsen controller in ps1 or ps2 mode c2.2 r3.2 fb2
ISL6353 25 september 15, 2011 fn6897.0 table 6 shows the definition of prog1. prog1 defines the maximum output current setting in the imax register of the ISL6353. table 7 shows the definition of prog2. prog2 defines the boot voltage, enable/disab le droop and the working mode for ps1. svid address setting the svid address of ISL6353 can be programmed by changing the resistor connected to the addr pin. table 8 shows the svid address definition. external control of vout and power state vset1/2, psi for additional design flexibility, the ISL6353 has 3 pins that can be used to set the output voltage and power state of the regulator with external signals independent of the serial communication bus register settings. table 6. definition of prog1 r prog1 ( ? ) i max 3-phase mode (a) i max 2-phase mode (a) i max 1-phase mode (a) 158 99 66 33 475 90 60 30 787845628 1100 81 54 27 1430 75 50 25 1740 69 46 23 2050 66 44 22 2370 60 40 20 2870 54 36 18 3480 51 34 17 4120 45 30 15 4750 39 26 13 table 7. definition of prog2 r prog2 ( ? )droop working mode at ps1 v boot (v) 158 enabled 1-phase ccm 0 475 enabled 1- phase ccm 1.20 787 enabled 1-phase ccm 1.35 1100 enabled 1- phase ccm 1.50 1430 enabled 2-phase ccm (3-phase configuration) 1-phase ccm (2-phase configuration) 1.50 1740 enabled 2-phase ccm (3-phase configuration) 1-phase ccm (2-phase configuration) 1.35 2050 enabled 2-phase ccm (3-phase configuration) 1-phase ccm (2-phase configuration) 1.20 2370 enabled 2-phase ccm (3-phase configuration) 1-phase ccm (2-phase configuration) 0 2870 disabled 2-phase ccm (3-phase configuration) 1-phase ccm (2-phase configuration) 0 3480 disabled 2 phase ccm (3-phase configuration) 1-phase ccm (2-phase configuration) 1.20 4120 disabled 2 phase ccm (3-phase configuration) 1-phase ccm (2-phase configuration) 1.35 4750 disabled 2 phase ccm (3-phase configuration) 1-phase ccm (2-phase configuration) 1.50 5360 disabled 1 phase ccm 1.50 6040 disabled 1 phase ccm 1.35 6650 disabled 1 phase ccm 1.20 7500 disabled 1 phase ccm 0 table 8. svid address definition r addr ( ? )address 158 0 475 1 787 2 1100 3 1430 4 1740 5 2050 6 2370 7 2870 8 3480 9 4120 a 4750 b 5360 c 6040 d table 7. definition of prog2 (continued) r prog2 ( ? ) droop working mode at ps1 v boot (v)
ISL6353 26 september 15, 2011 fn6897.0 vset1 and vset2 can be used to set the output voltage of the regulator. table 9 shows the available options. if vset1 and vset2 are connected to ground, the controller will refer only to the svid register setting to program the output voltage. if any other logic combination is used on vset1/2, the controller will ignore the svid register setting and progra m the output voltage based on table 8 for soft-start and steady state. the psi pin can be used to set th e power state of the regulator as indicated on table 10. if psi is connected to ground the controller will refer only to the svid register contents to set the power state. if psi is pulled high, the controller will enter the ps2 state. if psi is connected to a high impedance, the controller will enter the ps1 state. supported serial vid data and configuration registers the controller supports the fo llowing data and configuration registers. table 9. vset1/2 pin definition v boot from prog2 (v) vset1 vset2 output voltage 1.5 0 0 svid setting 1.5 0 1 1.35v 1.5 1 0 1.6v 1.5 1 1 1.65v 1.35 0 0 svid setting 1.35 0 1 1.2v 1.35 1 0 1.4v 1.35 1 1 1.45v 1.2 0 0 svid setting 1.2 0 1 1.1v 1.2 1 0 1.25v 1.2 1 1 1.3v 0 0 0 svid setting 0 0 1 1.05v 0 1 0 1.55v 0111.15v table 10. psi pin definition psi address 0 internal svid power state high-z ps1 1ps2 table 11. supported data and configuration registers index register name description default value 00h vendor id uniquely identifies the vr vendor. assigned by intel. 12h 01h product id uniquely identifies the vr product. intersil assigns this number. 35h 02h product revision uniquely identifies the revision of the vr control ic. intersil assigns this data. 05h protocol id identifies which revision of svid protocol the controller supports. 01h 06h capability identifies the svid vr capabilities and which of the optional telemetry registers are supported. 81h 10h status_1 data register read after alert# signal; indicating if a vr rail has settled, has reached vrhot condition or has reached icc max. 00h 11h status_2 data register showing status_2 communication. 00h 12h temperature zone data register showing temperature zones that have been entered. 00h 15h iout data register showing output current information. the voltage at the imon pin is digitized and stored in this register. 00h 1ch status_2_ lastread this register contains a copy of the status_2 data that was last read with the getreg (status_2) command. 00h 21h icc max data register containing the icc max the platform supports; set at start-up by resistor on prog1 pin. the platform design engineer programs this value during the design process. binary format in amps, for example 100a = 64h. refer to table 6 24h sr-fast slew rate normal. the fastest slew rate the platform vr can sustain. binary format in mv/s. i.e. 0ah = 10mv/s. 0ah 25h sr-slow is 4x slower than normal. binary format in mv/s. i.e. 02h = 2.5mv/s 02h
ISL6353 27 september 15, 2011 fn6897.0 26h vboot if programmed by the platform, the vr supports v boot voltage during start-up ramp. the vr will ramp to v boot and hold at v boot until it receives a new setvid command to move to a different voltage. refer to table 6 30h vout max this register is programmed by the master and sets the maximum vid the vr will support. if a higher vid code is received, the vr will respond with ?not supported? acknowledge. fbh 31h vid setting data register containing currently programmed vid voltage. vid data format. 00h 32h power state register containing the programmed power state. 00h 33h voltage offset sets offset in vid steps added to the vid setting for voltage margining. bit 7 is a sign bit, 0=positive margin, 1 = negative margin. remaining 7 bits are # vid steps for the margin. 00h = no margin, 01h = +1 vid step 02h = +2 vid steps... 00h 34h multi vr config data register that configures multiple vrs behavior on the same svid bus. vr1: 00h vr2: 01h table 11. supported data and configuration registers (continued) index register name description default value layout guidelines ISL6353 pin number symbol layout guidelines bottom pad gnd connect this ground pad to the ground plane throug h low impedance path. recommend use of at least 5 vias to connec t to ground planes in pcb internal layers. 1, 2, 3 sda, alert#, sclk follow intel recommendations. 4, 5, 6, 7, 22, 28, 36, 37, 38, 39 vr_on, pgood, imon, vr_hot#, prog1, pwm3, psi, vset1, vset2, ovp no special consideration. 8 ntc the ntc thermistor needs to be placed close to the therma l source that is monitored to determine the desired vr_hot# and thermal alert# toggling. recommend placing it at the hottest spot of the ISL6353 based regulator. 9 vw place the resistor and capacitor from vw to comp in close proximity of the controller.
ISL6353 28 september 15, 2011 fn6897.0 10, 11, 12 comp, fb, fb2 place the compensator components in general proximity of the controller 13, 14, 15 isen3, isen2, isen1 each isen pin has a capacitor (cisen) decoupling it to vsum n, then through another capacitor (cvsumn) to gnd. place cisen capacitors as close as possible to the controller and keep the following loops small: 1. any isen pin to another isen pin 2. any isen pin to gnd the red traces in the following drawing show the loops that need to minimized. 16, 17 vsen, rtn place the vsen/rtn filter in close proximity of the controller for good decoupli ng. route these signals differen tially from the remote sense location back to the controller. 18, 19 isumn, isump place the current sensing circuit in general proximity of the controller. place capacitor cn very close to the controller. place the ntc thermistor next to the phase 1 inductor so it senses the induct or temperature correctly. each phase of the power stage sends a pair of vsump and vs umn signals to the controller. run these two signals traces in parallel fashion. important: sense the inductor current by routing the sensing circuit to the inductor pads. if possible, route the traces on a different layer from the inductor pad layer and use vias to connect the traces to the center of the pads. if no via is allowed on the pad, consider routing the traces into the pa ds from the inside of the inductor. the following drawings show the two preferred ways of routing current sensing traces. if possible connect the traces to the inductor pad in only one place and isolate this connection from other planes of the same net that may be present on other layers. also make the connections a symmetric as possible for all phases. 20 vdd place the decoupling capacitor a close as possible to this pin. 21 vin place the decoupling capacitor a close as possible to this pin. layout guidelines (continued) ISL6353 pin number symbol layout guidelines v o isen3 l3 risen isen2 isen1 l2 l1 risen risen phase1 phase2 phase3 ro ro ro gnd cisen cisen cisen cvsumn vsumn inductor current-sensing traces vias inductor current-sensing traces
ISL6353 29 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com september 15, 2011 fn6897.0 for additional products, see www.intersil.com/product_tree products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog signal processi ng functions. go to www.intersil.com/products for a complete list of intersil product families. for a complete listing of applications, rela ted documentation and related parts, please see the respective device information p age on intersil.com: ISL6353 to report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff fits are available from our website at http://rel.intersil.com/reports/search.php 23 boot1 use a fairly wide trace (>30mil). avoid routing or crossing any sensitive analog signals near this trace. 24, 25 ug1, ph1 run these two traces in parallel with fairly wide traces (>30mil). avoid routing or crossing any sensitive analog signals near this trace. recommend routing the ph1 trace to the phase 1 high-side mosfet sour ce pins instead of general copper. 26 gnd connect this pin to ground right next to the cont roller or to the exposed pad underneath the controller. 27 lg1 use a fairly wide trace (>30mil). avoid routing or crossing any sensitive analog signals near this trace. 29 vddp place the decoupling capacitor a close as possible to this pin. 30 lg2 use a fairly wide trace (>30mil). avoid routing or crossing any sensitive analog signals near this trace. 31 gnd connect this pin to ground right next to the cont roller or to the exposed pad underneath the controller. 32, 33 ph2, ug2 run these two traces in para llel with fairly wide traces (>30mil). avoi d routing or crossing any sensitive analog signals near this trace. recommend routing the ph1 trace to the phase 1 high-side mosfet sour ce pins instead of general copper. 34 boot2 use fairly wide trace (>30mil). avoid routing or crossing any sensitive analog signals near this trace. 35 prog2 place resistor close to the controller. 40 addr place resistor close to the controller. revision history the revision history provided is for inform ational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest rev. date revision change 09/15/2011 fn6897.0 initial release. layout guidelines (continued) ISL6353 pin number symbol layout guidelines
ISL6353 30 september 15, 2011 fn6897.0 package outline drawing l40.5x5 40 lead thin quad flat no-lead plastic package rev 1, 9/10 typical recommended land pattern detail "x" top view bottom view side view located within the zone indicated. the pin #1 indentifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 id entifier is optional, but must be between 0.15mm and 0.27mm from the terminal tip. dimension b applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: (40x 0.60) 0.00 min 0.05 max (4x) 0.15 index area pin 1 pin #1 index area c seating plane base plane 0.08 see detail ?x? c c 5 6 a b b 0.10 m a c c 0.10 // 5.00 5.00 3.50 5.00 0.40 4x 3.60 36x 0.40 3.50 0.20 40x 0.4 0 .1 0.750 0.050 0.2 ref (40x 0.20) (36x 0.40 b package outline jedec reference drawing: mo-220whhe-1 7. 6 4

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